Field
The present disclosure relates to techniques for communicating optical signals. More specifically, the present disclosure relates to an optical cross-point macro-switch with a buffered switching matrix.
Related Art
Multistage Clos packet-switching networks are widely used in computing and telecommunications switching and routing systems to provide shared interconnectivity among many distinct endpoints or ports in these systems. In particular, these packet-switching networks are typically implemented as space-division switches that can scale to thousands of ports. However, because of input and output port contention, there is often an efficiency loss when such systems are scaled up, even in non-blocking Clos networks. This contention can be removed by using buffered switching nodes within each stage, so that all the intermediate nodes can store packets, thereby alleviating head-of-line blocking and/or output port blocking.
While fabricating buffered switches is usually difficult and expensive and it can be difficult to scale such architectures, the use of packet buffers before and/or after the switch has been demonstrated. The former is usually referred to as ‘input queuing’ or ‘virtual output queuing,’ and it typically removes head-of-line blocking so that any packet that can be routed from a specific input port does not have to wait in a queue for other packets destined for other destination ports to be routed first. Consequently, this approach can alleviate congestion at the input ports. Moreover, in the latter technique queues are used after the switch to reduce congestion within the network because of output-port congestion. Such memory buffers may also be used before and/or after the network in order to reduce head-of-line blocking, as well as to reduce switch contention because of output port blocking. However, the efficiency of the network is generally limited, and careful (and relatively complex) scheduling techniques may be needed to ensure that the network is not overloaded or pushed past its critical loading into an inefficient operating regime.
It is known that the use of memory buffers at all stages in a switch can lead to 100% switch utilization. However, it has proven difficult to implement such switches because each stage may have not only routing and forwarding functionality, but may also have memory buffers and rich connectivity to preceding and following switching/routing stages. Moreover, the need for memory at each stage may directly compete with the number of switches per stage and the number of stages that can be implemented. Therefore, the use of memory buffers at all stages in the switch may constrain the scalability of the switch.
Because of these challenges, pure space-division switching typically introduces too much competition between packets within the stages of a switching network and can cripple the overall system performance. Buffer memory is sometimes used before or after a switch to alleviate this blocking at the cost of scalability and packet routing/scheduling complexity. Furthermore, because of VLSI technology limitations, fully buffered switches are usually not scalable or practical to implement.
Researchers are investigating the use of optical interconnects and photonic switching to address some of these scalability limitations. For example, optical interconnects in VLSI switches can provide high-speed communication, and may permit large Clos packet-switching networks to be aggregated, e.g., by connecting smaller electrical switches with optical fiber links. While this architecture may facilitate the implementation of larger Clos packet-switching networks, it typically does not change the nature of the switching contention discussed previously. Indeed, the resulting Clos packet-switching networks usually have all the same congestion and inefficiencies, just at a larger scale.
Alternatively, photonic-switching (or optical-switching) products can eliminate the electrical switching stage in favor of a ‘transparent’ optical switch, in which data packets are sent via beams of light from any input port to an arbitrary output port. While the speed and latency of transmission of these photonic-switching products are low, the input port and the output port contention issues (and, thus, the inefficiencies) remain.
Hence, what is needed is a switch without the above-described problems.